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Espressif Systems /ESP32-S3 /SENSITIVE /INTERNAL_SRAM_USAGE_2

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Interpret as INTERNAL_SRAM_USAGE_2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0INTERNAL_SRAM_CORE0_TRACE_USAGE 0INTERNAL_SRAM_CORE1_TRACE_USAGE 0INTERNAL_SRAM_CORE0_TRACE_ALLOC 0INTERNAL_SRAM_CORE1_TRACE_ALLOC

Description

Internal SRAM configuration register 2.

Fields

INTERNAL_SRAM_CORE0_TRACE_USAGE

Set 1 to someone bit means corresponding internal SRAM level can be accessed by core0 trace bus.
INTERNAL_SRAM_CORE1_TRACE_USAGE

Set 1 to someone bit means corresponding internal SRAM level can be accessed by core1 trace bus.
INTERNAL_SRAM_CORE0_TRACE_ALLOC

Which internal SRAM bank (16KB) of 64KB can be accessed by core0 trace bus.
INTERNAL_SRAM_CORE1_TRACE_ALLOC

Which internal SRAM bank (16KB) of 64KB can be accessed by core1 trace bus.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data